1. Field of the Invention
The invention relates to the formation of conductive regions in silicon substrates.
2. Description of the Related Art
Integrated circuits manufactured on a silicon substrate comprise a series of interconnected active devices formed in and on the substrate. Each active device is formed by introducing impurities into a surface of the substrate, generally through the use of implantation or diffusion of the impurity, to vary the conductivity of specific regions of the substrate. The bulk substrate will generally be comprised of a material having first conductivity type, with the impurities selected to form regions in the substrate of opposite conductivity type or enhanced conductivity.
In forming some types of integrated circuits, particularly bipolar devices, it is desirable to provide layers of dopant which are "buried" below the surface of the device layer. Traditionally, a buried layer was formed in a substrate prior to the deposition of a layer of epitaxial silicon which was provided on the surface of a single crystal substrate and into which the active devices were formed. The buried region was formed by implantation or diffusion of the selected impurity in the substrate layer. In bipolar devices, buried layers are provided to reduce bulk resistance in collector regions. However, when the substrate is heated during processing, any buried materials which are formed in an epitaxial layer will diffuse back toward the surface of the epitaxial layer, thus reducing the effective depth that devices may be formed in the layer. In bipolar technologies, each diffusion step requires additional heating of the substrate, and hence dopants already present in the substrate or epitaxial layers will diffuse further. P type dopants are relatively quick diffusing materials and hence this back diffusion problem is particularly acute when the buried region is formed with p type dopants.
Advances in wafer processing technology have increased the popularity of so-called "bonded" wafers. In bonded wafer technology, two single-crystal substrates--a device substrate and handle substrate--are joined so that dopants can be introduced into a first surface of the device substrate to form an impurity region which subsequently becomes a buried region when the device substrate is bonded to the handle substrate at the first surface. In general, the handle wafer is comprised of a semiconductor having a first conductivity type, such as a p-type substrate, while the device substrate is comprised of a second conductivity type, such as an n-type substrate.
The handle wafer is "bonded" to the first substrate through any number of techniques. In some cases, Van der Waals forces may suffice to bond the surfaces (where tolerances are exacting, as disclosed in U.S. Pat. No. 4,638,552), or a thin oxide layer may be used between the surfaces (such as in U.S. Pat. No. 4,968,628), after which the substrates are heated to ensure bonding of the substrates to each other. This latter process is generally illustrated in FIGS. 1-4.
FIGS. 1-4 are cross sections generally showing the procedure for manufacturing an active device having a buried layer using a bonded wafer technique and junction isolation. Each of the active devices in an integrated circuit must be electrically isolated from the adjoining active region to prevent cross-over electrical effects between adjoining devices which would defeat overall operation of the circuit. The devices are thereafter connected to a series of metal or metal-alloy interconnect structures to complete the integrated circuit device.
FIG. 1 shows a p-type silicon substrate 10. Substrate 10 will have formed therein, for example, a p+ type region 12 by implantation or diffusion. Region 12 will become a buried layer formed in substrate 10 by selective diffusion. The surface of substrate 10 must be polished to a high tolerance surface finish, such as by chemical mechanical polishing, and may have a thin oxide layer formed thereon such as shown in FIG. 2. Oxide layer 14 is formed on the surface of substrate 10.
As shown in FIG. 3, a handle wafer 15 is thereafter bonded to substrate 10. Handle wafer 15 is generally an n-type substrate and will also have a thin layer of oxide formed on the surface to be bonded, such surface also being polished to a high degree of smoothness. The oxide on the handle wafer will contact oxide layer 14 on the surface of substrate 10. The wafers may then be heated to a temperature of about 1,000.degree. C. and held there for a period of time of about one hour. This causes the oxide layers to bond, thereby joining wafers 10 and 15. The resulting combined oxide layers 14' define the desired dielectric isolation thickness. Further processing can then occur on the backside 16 of substrate 10. Note that p+ region 12 becomes a buried region within the completed assembly.
As shown in FIG. 4, an n well 19 will be formed in substrate 10, and p+ emitter and collector contacts 17,18, and n+ base contact 20 may be formed to complete a PNP bipolar transistor.
While additional n+ regions 11 may be provided to serve as reverse biased PN junction lateral device isolation, the degree of isolation afforded by junction isolation is limited by collector-substrate leakage currents and collector-substrate capacitance. Several alternative isolation techniques have developed to prevent leakage currents from impeding device performance, including dielectric isolation and trench isolation.
The use of well regions or tubs--separate regions of impurities in which a device will be formed--is commonly used in numerous technologies, such as bipolar, complementary bipolar, and CMOS. This allows for device isolation and the provision of both PNP and NPN transistors on the same substrate.
While a single type of well may be formed in a substrate--i.e., all n-wells in a p type substrate--in some applications, it is necessary to provide wells of both conductivity types in the substrate. Wells are generally formed by implantation or diffusion of a doping impurity into the substrate. A particular type of well region which has been found useful is a so-called "retrograde" well. In a surface diffused well, the impurity concentration per unit volume decreases as one goes deeper into the substrate, away from the substrate surface. In a retrograde well, the concentration of the impurity relative to the substrate surface increases to a certain depth, then decreases. For example, normal diffusion involves deposition of the impurity into the surface, followed by a heating step wherein the dopant diffuses into the substrate and the concentration of the dopant varies with depth, with the concentration per unit area decreasing as diffusion continues.
The most common method for forming retrograde wells in CMOS technology is to use successive impurity implants at varying energies into the substrate. This process is illustrated in FIGS. 5-7.
FIG. 5 shows a semiconductor substrate 20 of a first conductivity type, such as a p-type substrate, in which complementary wells are to be formed. A photoresist mask layer 22 is deposited over substrate 20 and patterned to expose a window 23 for implantation of well dopant. Arrows 30 illustrate implantation of, for example an n type impurity such as arsenic or phosphorous. A number of successive implants at varying energies in a range of about 200 keV to 5 MeV are performed to achieve the desired profile of the well to be formed. As illustrated in FIG. 6, the high energy implants will form a well 34 with a graded concentration profile, wherein the concentration of the dopant will be greater in region 38 below the surface 21 of substrate 20 in region 36, closer to the surface.
As illustrated in FIG. 7, a masking layer 22 will be stripped and a second masking layer 24 deposited and patterned so that the complementary well region 44 may be formed in a similar fashion. Again, p well 44 has a dopant concentration greater in a region 48 below surface 21 of substrate 20. After implantation, the profile of the retrograde well may be smoothed out using an annealing process. With implantation of varying concentrations of the impurity to various depths, little or no diffusion of the impurity is required and a high degree of control of the well profile is possible. However, implantation of impurities into a substrate generally introduces a great deal of damage to the substrate. Retrograde wells may also be formed by diffusion by first implanting an impurity into the substrate to a depth below the surface of the substrate, then heating the substrate so that diffusion of the impurity takes place and the concentration varies with the highest concentration of material being at some depth below the surface of the substrate, rather than at the surface of the substrate itself. This method is limited by the depth to which one can implant an impurity and by the damage which occurs to a substrate through the initial implant.
Retrograde wells have been found to reduce many of the deleterious effects associated with short-channel, CMOS transistors. In bipolar transistors, the retrograde well characteristic is responsible for minimizing the gain of the inverse bipolar transistor. Further, the reduced well sheet resistance provided by the high peak concentration of the retrograde well reduces latch-up susceptibility.
The disadvantages to the approach of implanting successive layers of an impurity into the substrate include not only the damage which is introduced into a silicon wafer, but also the higher cost of multiple implants, the limited range of ion implant preventing deep retrograde wells from being formed by this method, and the implant-related defect generation from high energy implants.